1. Field of the Invention
The present relates to the packaging of semiconductor chips. More particularly, the present invention relates to a process and system for performing electrical bonding of semiconductor chips to packaging substrates.
2. Description of the Related Art
Recently, there has been tremendous advances in the fabrication of semiconductor devices, which have led to the continued development of smaller and smaller semiconductor chips. Unfortunately, the packaging of these smaller semiconductor chips is lagging behind in the ability to scale down the packaging dimensions. In fact, the 1997 National Technology Road Map for Semiconductors (NTRS), as published by the Semiconductor Industry Association (SIA) (1997), has identified packaging as a critical concern area, in that current packaging technologies fail to accommodate the continued scaling of on-chip interconnects.
Conventionally, semiconductor chips are connected to a package by way of wire bonds or solder bumps. As is well known, wire bonding requires that the semiconductor chip have bonding pads of a sufficient size to enable the wire bonding machines to connect the wire bonds between the semiconductor chip and the package. As a result, even though designers are able to scale down the physical size of the bonding pads resident on the semiconductor chip, the need to perform the appropriate wire bonding forces designers to layout physically larger bonding pads over the semiconductor chip.
The need for larger bonding pads over the semiconductor chip also has the down side of crowding the bonding pad arrangement, which necessarily requires reduced and staggered pad pitch arrangements. In certain high performance devices, the semiconductor chip will require a higher bonding pad count to meet particular input/output (I/O) requirements. Because the bonding pads on the semiconductor chip can only be reduced so much in view of the need to provide bonding pad surfaces that are of a size capable of receiving bonding wires, chip designers are typically forced to unnecessarily increase the size of chip.
When solder bumps are implemented to connect the semiconductor chip to a package, there is still a need to design bonding pad surfaces over the chip that will be large enough to receive the solder material. A further limitation associated with solder bumps is that the bonding pads over the chip must be separated from each other by a sufficient amount of space to avoid having shorts between adjacent bond pad overflows. Although solder bump chip-to-package connection does provide for a more dense arrangement of bonding pads relative to wire bonding, the solder bump bonding process does require more costly techniques for applying the solder material to the arrangement, connecting the chip to the package, and associated heat treatments to complete the bonding. In addition, solder bumping processes also have the down side of inducing well known alpha-particle damage. For instance, alpha-particle damage occurs when alpha-particles generated by lead solder bumps enter the device active area and generate electron hole pairs and the charge generated by the electron hole pairs upset the potential of the device, thus potentially causing failures.
In view of the foregoing, there is a need for processes and systems for more efficiently bonding semiconductor chips to package substrates. More particularly, there is a need for processes that will enable fast and efficient bonding connections between semiconductor chips and packages, wherein the packages can be reduced in size to a true chip-scale size.